Low-power low-voltage RF CMOS transceiver at 2.4 GHz

CMOS technology has reached its maturity. Therefore, design engineers used it for developing RF circuits. The advantages of CMOS technology are the higher integration, low-power consumption, low-voltage supply and low-cost compared with Bipolar technology. The use of CMOS process with low length for the channels of the MOSFETs is very important for high-frequency devices. This paper describes a radio frequency transceiver designed in UMC RF 0.18 μm CMOS process. This process has a poly and six metal layers, allowing the use of integrated spiral indutors (with a reasonable quality factor), high resistor value (a special layer is available) and a low-power supply of 1.8 V. The transceiver has a low noise amplifier that provides a 50 Ω input impedance, using a tuned load to provide high selectivity. The amplified RF signal is directly converted to the baseband with a double-balanced downconversion mixer, using a switched transconductor mixer. It's intended to drive the 50 Ω output load with an optional source follower device. Internal oscillator is a Phase-Locked Loop (PLL) working at 2.4 GHz, with a stable crystal oscillator reference of 20 MHz. The whole transceiver structure is illustrated in Fig. 1.